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ADM1041
APPENDIX A—CONFIGURATION TABLE
This table is included for users to program the part by function, rather than by register.
Table 45.
Description
Bit No.
Name
Bit
Bit
Bit
Option
Chip address is 1010xxx.
Second address bit
Target
(EEPROM programmable).
1
add1
b1
ADD0
xxx
device
0
0
0
L
H
Z
000
001
100
0
1
4
First address bit:
ADD0 = L, pin to ground.
ADD0 = H, pin to V DD .
ADD0 = Z, pin open.
Broadcast address.
1
1
1
X
L
H
Z
X
010
011
101
111
2
3
5
ALL
Config AC_OKLink and
PSONLink.
0
i2cmb
b0
Mode
0
1
Normal SMBus, microprocessor
SCL = AC_OK Link
SDA = PS ON Link
Configure AC SENSE to be
hardware derived or from
an SMBus command.
Configure PSON to be
hardware derived or from
an SMBus command.
6
7
up_AC_OK_m
up_pson_m
b6
0
1
b7
0
1
Mode
Hardware AC SENSE
Microprocessor support via SMBus
Mode
Hardware PS_ON
Micorporcessor support
via SMBus
Configure UV blanking to
be internally derived or
from AC_OKLink. (Set
opposite to i2cmb).
4
uvbm
b4
0
1
Mode
UVB follows AC_OKLink
UVB follows AC SENSE
Build FAULT or SMBAIert
signal. Allows a composite
interrupt to be constructed
by ORing up to 15 different
signals.
7–0
selcbd1
bn
7
6
signal
ovfault
uvfault
5
4
3
ocpt0 (ridethough timed out)
acsnsb
ocpf
This uses the CBD pin.
m_cbd_w is a μP writable
bit.
2
1
0
otp (mov5)
orfetokb
Share_OKb
7–1
selcbd2
7
6
5
4
3
2
1
0
V DD OK b
mfgl
mfg2
mfg3
mfg4
m_cbd_w
mfg5
Not used
Rev. A | Page 55 of 64
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